The OP07 has very low input offset voltage (75 μV maximum for OP07E) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP07 also features low input bias current (±4 nA for the OP07E) and high open-loop gain (200 V/mV for the OP07E). The low offset and high open-loop gain make the OP07 particularly useful for high gain instrumentation applications.

The wide input voltage range of ±13 V minimum combined with a high CMRR of 106 dB and high input impedance provide high accuracy in the noninverting circuit configuration. Excellent linearity and gain accuracy can be maintained even at high closed-loop gains. Stability of offsets and gain with time or variations in temperature is excellent. The accuracy and stability of the OP07, even at high gain, combined with the freedom from external nulling have made the OP07 an industry standard for instrumentation applications. The OP07 is available in two standard performance grades. The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow SOIC packages.   

Features:-

• Low VOS: 75 μV maximum 

• Low VOS drift: 1.3 μV/°C maximum 

• Ultrastable vs. time: 1.5 μV per month maximum 

• Low noise: 0.6 μV p-p maximum 

• Wide input voltage range: ±14 V typical 

• Wide supply voltage range: ±3 V to ±18 V 

• 125°C temperature-tested dice 

Specification:-

Related Document:-

 OP07 SMD Data Sheet